Recently, the progress in the technique for miniaturization of a semiconductor device is outstanding. For example, a memory mounted on an ASIC (application specific IC) product, such as RAM (random access memory) or ROM (read-only memory), is used for a large variety of uses, such as a high-end server, a high-end router or a mobile use and, in keeping up with the tendency to the increase of the capacity of the RAM, there is raised a demand for a higher density (a smaller area) and for a higher operating frequency.
Under this situation, the so-called precharge operation, which directly follows the write operation and which completes the write operation of a memory cell by causing a full-swing of the bit line pair to which the memory cell is connected, is one of the factors limiting the frequency characteristic of the RAM.
The RAM which can meet the request on the part of users cannot be achieved without speedup of the cycle of the write cycle. However, the state-of-the-art RAM suffers from a gap between the characteristics for the write cycle and those for the read cycle. This difference tends to be more apparent with increase in the memory capacity of the RAM.
FIG. 9 shows characteristics of write cycle and read cycle in a RAM, in a tabulated form. This figure shows that the write cycle takes time longer by 6 to 15% than the read cycle, with the difference being 200 ps to 1.1 ns.
FIG. 10 is a timing chart for illustrating the internal operation in a conventional typical synchronous RAM. A word line pulse driving system is used in which, after rising of an external input clock (CLK), an internal reference clock (ICLK) is generated to set a selected word line (WL) to an activated state only for a predetermined period of time. The pulse timing is set from the perspective of assuring a variety of operational margins of the RAM, such as assuring                time of inverting a cell (write operation), and        cell read margin (read operation).        
As long as the write cycle is concerned, the timing is set so that one of the voltages applied to one of the bit lines of a bit line pair is changed from the VDD level to the GND level, with a ‘full-swing’ operation, as indicated at ‘1’ in FIG. 10 in order that a stabilized voltage level will be obtained despite a variety of sorts of variable elements in cell inversion, while the voltage applied to the other bit line remains at VDD. The Variable elements in cell inversion includes process-related elements or variable elements in the cells or in loads on bit lines.
On the other hand, as for a read cycle, the timing is set so that a ‘half-swing’ operation, as indicated at ‘2’ in FIG. 10, will be carried out because it is only sufficient to send the difference potential, as needed by an I/O line pair (DLDT/DLDB) of a sense amplifier section used for amplifying the level of the memory cell information once the information has been supplied to the bit lines.
In general, from the perspective of simplifying the peripheral circuit, the write read control clock and the precharge are of the same timing. In FIG. 10, WEB denotes a write enable signal, PC a control signal for controlling the precharging of bit lines, YSL a control signal for on/off control of a column switch, an I/O line pair a wired contact as selected by a column switch YSL, SAPC a precharging signal for the sense amplifier section, SES a sense amplifier enabling signal, DLDT/B an I/O line pair of the sense amplifier section, and DO denotes a data output. The configuration of, for example, the bit line pair, sense amplifier and the I/O line pair of the sense amplifier section is to be in keeping with the routine DRAM configuration as well known in the art. For example, reference may be made to the disclosure of the Patent Documents 2 and 3. The I/O line pair DLDT/B of the sense amplifier section, for example, is equivalent to a line pair IO/IOB connected via a column switch to a bit line pair in the sense amplifier section.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-04-326270
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2000-40370A
[Patent Document 3]
JP Patent Kokai Publication No. JP-A-10-55673